Translation, permissions and cache coherence
This required 20–28-hour package replaces the former two-hour translation simulator exercise: lessons and prediction 5–7, implementation and experiments 10–14, assessment and delayed repair 5–7. Estimates are author planning assumptions awaiting learner pilots. Existing demand paging, replacement, allocators, COW, huge pages and NUMA practice remains required. See the reconciled semester workload.
Prerequisite bridge
Bring Semester 04 integer representation, capacity contracts and measurement discipline. Divide 0x2345 by 4096 into page and offset, explain a dictionary key pair, and draw an LRU list. If needed, use 1–2 hours of the lesson allocation to repair these skills before implementation.
Learning sequence
- Translation outcomes.
- Address spaces and stale translations.
- Cache experiments and accounting.
- Prediction practice, runnable lab, VM1–VM6 and calibration.
Selective primary resources
Read OSTEP on TLBs for translation lookup and permission checks. Consult OSTEP replacement policies to distinguish resident-page replacement from translation-cache eviction. Use Linux cache/TLB flushing interfaces to connect mapping changes with invalidation obligations; this lab models one CPU and cannot demonstrate a real multiprocessor shootdown.
Sources checked on 2026-10-23. The original OSTEP/Operating System Concepts selections remain the backbone. No book purchase or full-book conversion is needed. The simulator and exercises are original teaching material and do not claim ISA conformance.