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Translation outcomes and permission checks

What this concept is​

An address translation has several independent questions: does a mapping exist, is the requested operation permitted, is a frame resident, and is its translation cached? A TLB hit answers only the last question. The lab returns cache outcome separately from access outcome.

Why it matters here​

Conflating a cache miss with a page fault makes both correctness and cost models misleading. A cache miss may be resolved using a resident page-table entry. A denied operation must fail even when the translation is cached.

Concrete example​

For 4 KiB pages, 0x2345 is VPN 2 plus offset 0x345. With frame 9 and read permission, a read yields 0x9345. A subsequent write hits the cached entry but reports protection with no physical address. With no mapping it reports unmapped; with a readable mapping and no frame it reports nonresident.

Common confusion / misconception​

Nonresident does not mean necessarily disk-backed. The model stops before fault handling; a real handler might allocate/zero-fill, fetch data, perform COW or reject access. The lab checks permission before residency, but this chosen precedence is not a promise about every processor’s exception rules.

How to use it​

Create separate cache and access-result fields. Preserve offset on every successful translation. Never return a usable physical address for an unsuccessful access. For a mapped nonresident page, record the fault, explicitly install a frame, then retry; do not silently classify the first request as success.

Check yourself​

Can a TLB hit produce protection failure? Yes. Can a TLB miss complete without storage access? Yes. Does this simulator provide data from memory? No: it only returns the address or fault classification.

Mini drill or application​

Predict 0x2FFF and 0x3000 under different mappings. Give one hit/failure case and one miss/success case. Explain why offset wrap changes the page rather than carrying into an unrelated cached frame.

Read this only if stuck​

Review the address-space abstraction in OSTEP chapter 13, then label mapping, permission, residency and cache state separately.