Translation assessment calibration

• VM1: 0x2345 becomes 0x9345 for frame 9; 0x2FFF becomes 0x9FFF. 0x3000 belongs to VPN 3. Checking only offset zero misses a dropped-offset bug.
• VM2: a warmed read-only entry can yield hit/protection on write. A resident uncached mapping yields miss/ok. Permission precedes residency in this model; the learner must not universalize that ordering. Installing a frame requires an explicit operation before retry.
• VM3: the two-entry trace 1,2,1,3,1 is miss,miss,hit,miss,hit. The final hit distinguishes LRU from FIFO here. Running the reference earns no implementation credit. Ask for the independent list oracle or hand trace.
• VM4: changing the frame or permissions invalidates the exact ASID/VPN. Dropping ASID from the key can expose another process’s translation. Missing invalidation retains the old tuple even after the page table changes. Require a failing trace and a repaired run.
• VM5: every valid request counts exactly once; walks equal misses under this abstraction. No timing or disk count is returned. Translation-cache eviction does not remove a resident page. A single-CPU simulation does not establish multiprocessor invalidation correctness.
• VM6: use new frames, permissions and ASIDs in the delayed case. A strong answer explains where synchronization would be required if accesses and remaps could run concurrently; “just clear the cache” without scope or ordering is insufficient.

For each failed gate, revisit its lesson and retest with a different case. Do not substitute a polished copied explanation for independently defended evidence.