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Book Exercise Lanes

This module's exercise system is book-driven, with a strong hands-on component. Use these local chunks and the practice labs together for targeted volume after you have already learned the concept from the guide.

How To Use This Page​

  1. Finish the relevant concept page first.
  2. Run the matching practice lab or do at least one bit-split / page-walk / simulator drill on your own paper.
  3. Only then open the matching exercise lane below.
  4. Keep a mistake log with tags such as wrong VPN/offset split, missed TLB miss vs page fault distinction, LRU implemented as FIFO, confused minor/major fault, forgot CoW, wrong mmap flavor, ignored external fragmentation, or assumed THP is always good.

Lane 1: Address Translation and Paging Math​

Use this lane when the issue is translating a virtual address, drawing a page-table walk, or reasoning about page sizes.

Target outcomes:

  • 10 virtual-to-physical translations solved by hand with explicit VPN/offset split
  • 4 multi-level page-table walks on paper (4-level x86-64 style)
  • 4 page-size-tradeoff comparisons (4 KiB vs 2 MiB, PTE memory cost, TLB coverage)
  • 2 written "inverted vs forward page-table" tradeoff analyses

Lane 2: TLB, Faults, and Replacement Policies​

Use this lane when you can translate but cannot reason about cost - TLBs, faults, and replacement.

Target outcomes:

  • 6 TLB cost analyses (hit rate -> effective access time)
  • 6 replacement-policy simulations by hand (OPT, FIFO, LRU, Clock) on distinct reference strings, including at least one that exhibits Belady's anomaly
  • 4 minor-vs-major fault distinctions on real perf stat outputs
  • 2 thrashing diagnoses from vmstat / PSI timelines
  • 1 written "why exact LRU is not implemented and what Clock does instead"

Lane 3: Allocators and Fragmentation​

Use this lane when the kernel / allocator layer is the source of confusion, or when your RSS / CPU numbers do not match your expectations.

Target outcomes:

  • 4 buddy-allocator traces (split / coalesce on explicit request sequences)
  • 4 slab allocator reasoning problems (which cache? why fixed size? what if a size class is wrong?)
  • 4 userland allocator comparisons (ptmalloc vs jemalloc vs tcmalloc) with written RSS / throughput predictions, validated by benchmark
  • 2 written fragmentation post-mortems (one internal, one external) from real /proc/slabinfo or malloc_stats output

Lane 4: Practical VM Effects (CoW, mmap, Huge Pages, NUMA)​

Use this lane when you know the mechanisms but cannot predict how a program interacts with them.

Target outcomes:

  • 4 fork behavior predictions before running them, then verified via /proc/$pid/smaps
  • 4 mapping-flavor problems (choose and justify private vs shared, anonymous vs file-backed)
  • 3 huge-page tradeoff analyses on real workloads (where THP helps, where it hurts)
  • 2 NUMA case studies with numastat or numactl --hardware output
  • 1 written diagnosis pipeline: "given these five observations from /proc/meminfo, vmstat, and perf, what is the memory problem?"

Self-Curated Problem Set​

Build a custom set with these minimums:

  • 5 translation / page-walk problems (mix of 2-level and 4-level)
  • 5 replacement-policy simulations on distinct reference strings
  • 5 allocator-behavior predictions validated on real benchmarks
  • 5 CoW / mmap predictions validated on real programs
  • 3 production-style "diagnose this memory symptom" narratives

Completion Checklist​

  • Completed at least one lane in full
  • Retained actual mistakes, their evidence and corrections; if none occurred, label a deliberately faulty example and show how to detect it. No minimum personal-error count.
  • Wrote at least 6 page-table walks by hand with no reference
  • Ran at least 4 of the practice-lab experiments end-to-end with real perf / /proc data
  • Diagnosed at least 3 real or simulated memory symptoms (TLB-heavy, fault-heavy, fragmentation-heavy) to the right concept
  • Wrote a one-paragraph paradigm triage: "I would tune/change X because Y, given these measurements"

Required translation-contract extension​

Complete Translation, permissions and cache coherence and all VM1–VM6 gates. This 20–28-hour package replaces the former two-hour translator lab; original memory-management practice remains required.