Learning Resources
This module is populated from the local chunked books in library/raw/semester-04-systems-programming/books and from a short list of validated external resources. Use this page as a source map, not as an instruction to read everything.
Source Stack
| Source | Role | How to use it in this module |
|---|---|---|
| Computer Organization and Design (Patterson & Hennessy) | Primary teaching source | Default escalation for ISA, arithmetic, pipelining, cache, virtual memory, and I/O |
| CODE (Petzold) | Conceptual foundation | Use when the Patterson treatment is too abstract and you want a from-scratch, hardware-first picture |
| The C Programming Language (K&R) | Cross-reference | Use when mapping C constructs onto the assembly you are reading |
| SICP | Peripheral | Occasional reinforcement for the abstract-machine mental model; not the main path for this module |
Note: Computer Systems: A Programmer's Perspective (CSAPP) is referenced widely in the field but is not available in the local book chunks. If you want a second take on caches, virtual memory, and exceptions at the same depth as Patterson, CSAPP is the best alternative external source.
Resource Map by Cluster
Cluster 1: The ISA and the Stored-Program Machine
| Need | Best local chunk | Why |
|---|---|---|
| what an ISA is | COD 2.1 Introduction | Cleanest first pass at "the computer's language" |
| operands and registers | COD 2.3 Operands of the Computer Hardware | Grounds the idea of a register file |
| calling convention | COD 2.8 Supporting Procedures in Computer Hardware | Best explanation of stack frames |
| x86 specifics | COD 2.17 Real Stuff -- x86 Instructions | Pragmatic side-by-side with MIPS |
| ARM specifics | COD 2.16 Real Stuff -- ARM Instructions | Useful comparative read |
| from C to machine | COD 2.12 Translating and Starting a Program | End-to-end view of compilation and linking |
| hardware ground truth | CODE: Registers and Busses | Low-level construction of the register file |
Cluster 2: Arithmetic, Logic, and Control
| Need | Best local chunk | Why |
|---|---|---|
| two's complement | COD 2.4 Signed and Unsigned Numbers | Clean derivation of the representation |
| addition and subtraction | COD 3.2 Addition and Subtraction | Establishes flag semantics |
| multiplication | COD 3.3 Multiplication | Shift-and-add baseline, Booth cited |
| decisions and branches | COD 2.7 Instructions for Making Decisions | Canonical branch taxonomy |
| floating point | COD 3.5 Floating Point | Best IEEE-754 walkthrough in the book |
| ALU built from scratch | CODE: The Arithmetic Logic Unit | Reinforces what an ALU is by building one |
Cluster 3: Memory Hierarchy and Cache
| Need | Best local chunk | Why |
|---|---|---|
| why the hierarchy exists | COD 5.1 Introduction | Best first pass on locality and levels |
| cache geometry | COD 5.2 The Basics of Caches | Full cache mechanics, with examples |
| associativity and replacement | COD 5.2 Caches (Part 6) | Trade-offs across geometries |
| measuring cache performance | COD 5.3 Measuring and Improving Cache Performance | Classic miss-rate analysis |
| cache on real hardware | COD 5.10 Real Stuff -- Nehalem/Opteron Memory Hierarchies | Grounds the model in real chips |
Cluster 4: Pipelining and Parallel Execution
| Need | Best local chunk | Why |
|---|---|---|
| pipelining intuition | COD 4.5 An Overview of Pipelining | Best first motivation |
| datapath and control | COD 4.6 Pipelined Datapath and Control | Walks the stages with actual registers |
| data hazards | COD 4.7 Data Hazards -- Forwarding vs Stalling | Canonical load-use discussion |
| control hazards | COD 4.8 Control Hazards | Prediction, resolution, and misprediction cost |
| real superscalar core | COD 4.11 Opteron X4 Pipeline | Anchors the abstract model to a real core |
| SIMD and vector | COD 7.6 SISD/MIMD/SIMD/SPMD and Vector | Short and clear SIMD introduction |
Cluster 5: I/O and Virtual Memory Basics
| Need | Best local chunk | Why |
|---|---|---|
| virtual memory | COD 5.4 Virtual Memory | Standard address-translation walkthrough |
| page tables and TLB | COD 5.4 Virtual Memory (Part 5) | Focused on the TLB's role |
| protection and permissions | COD 5.4 Virtual Memory (Part 8) | PTE bits and privilege |
| exceptions | COD 4.9 Exceptions | How the CPU enters the OS |
| MMIO and buses | COD 6.5 Connecting Processors, Memory, and I/O Devices | Topology of the I/O subsystem |
| performance framing | COD 7.10 Roofline -- A Simple Performance Model | Unifies memory- vs compute-bound reasoning |
| early performance framing | COD 1.4 Performance | CPU performance equation baseline |
External Resources (validated)
- Compiler Explorer (godbolt.org) -- interactive compiler/assembly explorer, the single most useful external tool for this module.
- Agner Fog -- Software optimization resources -- microarchitecture manuals and instruction-level tables for x86.
- Agner Fog -- "The microarchitecture of Intel, AMD, and VIA CPUs" -- deep detail on how modern cores really work.
- Ulrich Drepper -- "What Every Programmer Should Know About Memory" (LWN) -- the canonical deep dive on caches, TLB, and DRAM.
- MIT 6.004 Computation Structures (OCW) -- lectures and problem sets that cover much of this module from the ground up.
Use Rules
- For any topic, start with the concept page. Only open a book chunk when the concept page and practice sheet have not fixed the gap.
- Use CODE when the Patterson treatment assumes too much; use CODE first if you have never seen hardware at all.
- When chasing a performance question, favour measurement (perf, objdump, Compiler Explorer) over reading. Books describe the model; your machine tells you what is actually happening.
- Save CSAPP as an optional second source -- it is not available locally in this repo's chunks.