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Module Quiz

Complete this quiz after finishing all concept and practice pages. Save your answers before opening separate quiz calibration.

Current Module Questions​

Question 1: Fetch-Decode-Execute​

What are the four phases of the fetch-decode-execute cycle, and which piece of architectural state is updated at the end of each instruction?

Question 2: RISC vs CISC​

Why is "x86 is CISC so it is slow" a misleading claim in 2025?

Question 3: Calling Convention​

On x86_64 Linux, which register holds the first argument to a function, which holds the return value, and which register is the stack pointer? Name one caller-saved and one callee-saved register.

Question 4: Disassembly Recognition​

A compiled loop looks like: add %rdi,%rdi ... addq $1,(%rdi); add $4,%rdi; cmp %rdx,%rdi; jne .L1. What C construct did this likely come from?

Question 5: Two's Complement and Flags​

Given the 8-bit addition 0x7F + 0x01, what is the result and what do the Z, S, C, O flags get set to?

Question 6: Performance Prediction -- Row-Major vs Column-Major​

For an N=4096 array of double (32 MiB) on an x86_64 desktop, predict roughly the ratio between row-major and column-major traversal time for a sum, and justify the number using 64-byte cache lines.

Question 7: Performance Prediction -- Cache Miss Cost​

If an inner loop takes 1.0 ns per iteration when its working set fits in L1, and 6.0 ns per iteration when it does not, roughly how many DRAM misses per iteration does the second regime imply? Assume a DRAM miss costs ~100 ns.

Question 8: Pipeline Hazards​

In a classic 5-stage pipeline with forwarding, why does a load followed immediately by a consuming ALU op still cost one bubble, while two dependent ALU ops do not?

Question 9: Branch Misprediction​

Given a loop whose back-edge is taken n-1 times and not taken once, how many mispredicts does an ideal branch predictor incur? How does the answer change for a random if (a[i] > k) inside the loop?

Question 10: SIMD and Unrolling​

A scalar FP reduction loop with one accumulator sustains one FMA per 4 cycles. Explain, in terms of dependency chains, why breaking it into 4 accumulators can give a 4x speedup even without using SIMD.

Question 11: Cache Geometry​

Decompose the address 0x0000_0000_0004_ABCD into tag, set, offset for a 32 KiB, 8-way, 64-byte line L1.

Question 12: Virtual Memory​

Why can a TLB miss cost more than the memory access it is translating?

Question 13: Performance Prediction -- TLB​

A program sweeps 2 GiB of memory one byte per 4 KiB page. What mechanism slows it down, and which OS-level knob most directly reduces that cost?

Question 14: Hardware-Software Contract​

State Amdahl's law and use it to explain why a workload that is "95% parallel" cannot exceed 20x speedup.

Question 15: Roofline​

A kernel has arithmetic intensity 0.25 flops/byte. Peak compute is 128 GFLOPS; DRAM bandwidth is 32 GB/s. What is the attainable performance, and is the kernel compute- or memory-bound?

Interleaved Review Questions​

Prior Module Question 1​

Why is int *p = (int *)0x400000 not a safe way to access memory in a modern Linux process?

Prior Module Question 2​

What is the difference between stack and heap allocation in C?

Prior Module Question 3​

What does const T *p promise compared to T * const p?

Prior Module Question 4​

Why does endianness matter when serializing a uint32_t to bytes?

Prior Module Question 5​

What does -O2 typically do beyond -O0?

Self-Assessment and Remediation​

Mastery Level (90-100% correct):

  • Retrieval is strong; complete all module and semester evidence gates before advancing.

Proficient Level (75-89% correct):

  • Review the missed concept pages and redo the relevant practice experiment with measured numbers.

Developing Level (60-74% correct):

  • Rework the Memory Hierarchy Workshop and the Pipelining Clinic. Rebuild the mental cost model for a cache miss and a mispredict before advancing.

Insufficient Level (<60% correct):

  • Return to Cluster 1 and walk through disassembly for five simple functions cold. Then repeat this quiz.

Progression boundary​

Quiz performance calibrates retrieval and reasoning. It does not replace runnable work, changed-case transfer, the module assessment or required semester evidence. Consult practice calibration for the additional independent cases.