Reference and Selective Reading
You do not need to read the source books front-to-back for this module. Use the concept pages and practice pages first. Open these local chunks only when you need alternate exposition, more worked examples, or a deeper exercise lane.
Source Roles
| Source | Role | Why it is here |
|---|---|---|
| Computer Organization and Design (Patterson & Hennessy) | Primary teaching source | Best overall coverage of ISAs, arithmetic, pipelining, caches, virtual memory, and I/O |
| CODE (Petzold) | Conceptual foundation | Builds the same ideas from electrical first principles; useful when Patterson feels abstract |
| The C Programming Language (K&R) | Cross-reference | Source of the C constructs you are reading in disassembly |
| SICP | Peripheral | Occasional reinforcement of the abstract-machine viewpoint; not the main path |
Note: Computer Systems: A Programmer's Perspective (CSAPP) is not part of the local chunks. If you need a second take on caches, virtual memory, or linking, that is the recommended external source.
Read Only If Stuck
ISA and the Stored-Program Machine
- COD: 1.1 Introduction
- COD: 1.2 Below Your Program
- COD: 1.3 Under the Covers
- COD: 2.1 Introduction
- COD: 2.3 Operands of the Computer Hardware
- COD: 2.5 Representing Instructions in the Computer
- COD: 2.8 Supporting Procedures
- COD: 2.12 Translating and Starting a Program
- COD: 2.13 A C Sort Example
- COD: 2.14 Arrays versus Pointers
- COD: 2.16 Real Stuff -- ARM
- COD: 2.17 Real Stuff -- x86
- CODE: Registers and Busses
- CODE: CPU Control Signals
- CODE: Loops, Jumps, and Calls
Arithmetic, Logic, and Control
- COD: 2.4 Signed and Unsigned Numbers
- COD: 2.6 Logical Operations
- COD: 2.7 Instructions for Making Decisions
- COD: 3.1 Introduction
- COD: 3.2 Addition and Subtraction
- COD: 3.3 Multiplication
- COD: 3.4 Division
- COD: 3.5 Floating Point
- COD: 3.5 Floating Point (Part 3)
- CODE: The Arithmetic Logic Unit
- CODE: Floating-Point Approximation and Math Coprocessors
Memory Hierarchy and Cache
- COD: 5.1 Introduction
- COD: 5.1 Introduction (Part 3)
- COD: 5.2 The Basics of Caches
- COD: 5.2 Caches (Part 6)
- COD: 5.2 Caches (Part 9)
- COD: 5.3 Measuring and Improving Cache Performance
- COD: 5.8 Parallelism and Memory Hierarchies -- Cache Coherence
- COD: 5.10 Real Stuff -- Memory Hierarchies
- COD: 5.11 Fallacies and Pitfalls
Pipelining and Parallel Execution
- COD: 4.5 Overview of Pipelining
- COD: 4.6 Pipelined Datapath and Control
- COD: 4.7 Data Hazards
- COD: 4.8 Control Hazards
- COD: 4.11 Real Stuff -- Opteron Pipeline
- COD: 7.6 SIMD and Vector
- COD: 3.6 Parallelism and Computer Arithmetic -- Associativity
I/O and Virtual Memory
- COD: 4.9 Exceptions
- COD: 5.4 Virtual Memory
- COD: 5.4 Virtual Memory (Part 5)
- COD: 5.4 Virtual Memory (Part 8)
- COD: 5.4 Virtual Memory (Part 11)
- COD: 6.5 Connecting Processors, Memory, and I/O
- COD: 6.5 (Part 5)
- CODE: Peripherals
Performance Framing
Optional Deep Dive
- COD: 1.5 The Power Wall
- COD: 1.6 Uniprocessors to Multiprocessors
- COD: 5.6 Virtual Machines
- COD: 7.7 Introduction to GPUs
External Deep Dive
- Compiler Explorer (godbolt.org)
- Agner Fog -- Software optimization resources
- Agner Fog -- "The microarchitecture of Intel, AMD, and VIA CPUs"
- Ulrich Drepper -- "What Every Programmer Should Know About Memory"
- MIT 6.004 Computation Structures (OCW)
Concept-to-Source Map
| Primary concept | Best source if stuck | Why this source |
|---|---|---|
| ISA, RISC vs CISC, fetch-decode-execute | COD 2.1 Introduction | Cleanest architectural framing |
| Registers, PC, stack pointer | COD 2.8 Supporting Procedures | Canonical stack-frame discussion |
| From C to assembly | COD 2.13 A C Sort Example | End-to-end source -> assembly walkthrough |
| ALU / arithmetic | COD 3.2 Addition and Subtraction | Direct derivation of the adder and flags |
| Control flow at the machine level | COD 2.7 Decisions | Best branch and compare discussion |
| Memory hierarchy | COD 5.1 Introduction | Cleanest statement of locality |
| Cache organization | COD 5.2 Caches (Part 6) | Associativity and replacement in depth |
| Cache-aware programming | COD 5.3 Measuring and Improving Cache Performance | Turns cache model into action |
| Five-stage pipeline | COD 4.5 Overview of Pipelining | Best first exposure to pipelining |
| Hazards | COD 4.7 Data Hazards | Canonical load-use and forwarding analysis |
| Virtual memory | COD 5.4 Virtual Memory | Standard multi-level translation story |
| Hardware-software contract | COD 7.10 Roofline | Best unifying performance model |