Module 3: Computer Organization & Architecture: Mistake Clinic

This clinic turns wrong moves into reusable judgment. Use it after each practice page and again before the quiz or checkpoint.

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Module-Specific Mistake Radar

Start with these traps. Replace or extend them with real mistakes from your own work.

Mistake to look for	Where it shows up	Symptom	Repair evidence
Finishing ISA and Disassembly Lab with only a final answer	ISA and Disassembly Lab	The work has no failed case, trace, test, proof gap, or design stress point.	Add the smallest broken example and show the repair that changes the result.
Finishing Memory Hierarchy and Cache Workshop with only a final answer	Memory Hierarchy and Cache Workshop	The work has no failed case, trace, test, proof gap, or design stress point.	Add the smallest broken example and show the repair that changes the result.
Finishing Pipelining and Optimization Clinic with only a final answer	Pipelining and Optimization Clinic	The work has no failed case, trace, test, proof gap, or design stress point.	Add the smallest broken example and show the repair that changes the result.
Finishing Code Katas with only a final answer	Code Katas	The work has no failed case, trace, test, proof gap, or design stress point.	Add the smallest broken example and show the repair that changes the result.
Treating Instruction Set Architectures, RISC vs CISC, and the Fetch-Decode-Execute Cycle as vocabulary instead of a tool	Instruction Set Architectures, RISC vs CISC, and the Fetch-Decode-Execute Cycle	The explanation names the concept but cannot decide between two cases.	Write one example, one non-example, and the rule that separates them.
Treating Registers, the Program Counter, and the Stack Pointer as vocabulary instead of a tool	Registers, the Program Counter, and the Stack Pointer	The explanation names the concept but cannot decide between two cases.	Write one example, one non-example, and the rule that separates them.

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Practice Mistake Checks

Pull any miss from these checks into your mistake log.

ISA and Disassembly Lab

Source: practice/01-isa-and-disassembly-lab.md

For each statement, identify the error:

1. "x86 is CISC, so every x86 instruction is slow."
2. "At -O0 the compiler's output shows what the compiler really does."
3. "ret jumps to the instruction after the most recent call in the source file."
4. "Registers are faster than L1 cache because they are cached closer to the core."
5. "Function pointers are free to call because a pointer is just an address."

Memory Hierarchy and Cache Workshop

Source: practice/02-memory-hierarchy-and-cache-workshop.md

For each statement, identify the error:

1. "An SSD's low latency means cache hierarchy is no longer important."
2. "Prefetching always helps because it brings data in earlier."
3. "If two threads write different variables they cannot interfere."
4. "std::list<T> is faster than std::vector<T> for insertion-heavy workloads regardless of size."
5. "Cache misses are rare for code that has good big-O complexity."

Pipelining and Optimization Clinic

Source: practice/03-pipelining-and-optimization-clinic.md

For each statement, identify the error:

1. "Pipelining halves cycle time."
2. "A taken branch is a performance cost."
3. "Forwarding eliminates all data hazards."
4. "Out-of-order execution means programs are no longer deterministic."
5. "-O3 auto-vectorizes any loop."

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Repair Protocol

For each real mistake:

1. Reproduce the failure on the smallest example, trace, proof, query, command, or design sketch.
2. Name the hidden assumption.
3. Repair the artifact.
4. Save evidence that changed: failing then passing test, corrected proof step, revised diagram, safer command, benchmark, or review note.
5. Add one retrieval card beginning with Check... before... or Do not use... when....

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Mistake Log

Date	Mistake	Symptom	Root cause	Repair evidence	Retrieval card
Starter	Pick one radar row above	Explain how it would fail in this module	Name the assumption	Add a counterexample or corrected artifact	Write the card before closing the page

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Completion Standard

• At least five real mistakes are logged.
• At least two mistakes include a counterexample or failing test.
• At least one mistake connects to an older semester skill.
• At least one correction changes code, a proof, a diagram, a command transcript, a query, or a design decision.