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Book Exercise Lanes

This module's exercise system is book-driven and measurement-driven. Use these local chunks for targeted volume after you have already learned the concept from the guide. Whenever possible, pair paper exercises with a small benchmark or disassembly session.

How To Use This Page​

  1. Finish the relevant concept page first.
  2. Solve at least one problem of your own from memory.
  3. Only then open the matching exercise lane.
  4. For each bench-able problem, produce an actual measurement or disassembly. Architecture without numbers becomes mythology.
  5. Keep a mistake log with tags such as wrong cache geometry, ignored TLB, confused latency with throughput, mismatched caller/callee-saved, or forgot pipeline bubble.

Lane 1: ISA, Operands, and Disassembly​

Use this lane when your main problem is reading assembly and mapping constructs back to source.

Target outcomes:

  • 10 annotated disassemblies (C + generated x86_64 or RISC-V, every instruction labelled)
  • 5 ABI analyses showing which registers hold arguments, results, and saved state
  • 3 short programs built from scratch where you predict the assembly before compiling

Lane 2: Arithmetic, Flags, and Control Flow​

Use this lane when you can read assembly but still guess about flag behaviour, signed vs unsigned comparison, or branch shape.

Target outcomes:

  • 8 hand-computed flag states verified under gdb
  • 4 rewrites turning branchy code into branchless equivalents, measured before and after
  • 2 FP experiments exercising denormal flush, FMA, and -ffast-math trade-offs

Lane 3: Memory Hierarchy and Cache​

Use this lane when cache behaviour feels mysterious rather than predictable.

Target outcomes:

  • 6 address decompositions (tag/set/offset) for mixed cache geometries
  • 3 hit/miss traces classified by miss type
  • 1 full row-major vs column-major matrix sum benchmark with measured ratio and perf counters
  • 1 blocked matrix multiply benchmark showing speedup over the naïve version

Lane 4: Pipelining, Superscalar, and Parallelism​

Use this lane when a program's performance stops tracking instruction counts.

Target outcomes:

  • 4 hazard-analysis walkthroughs for short instruction streams
  • 2 measured microbenchmarks comparing one-accumulator vs multi-accumulator reductions
  • 1 branch-predictability study (sorted vs random input) with perf data
  • 1 SIMD vs scalar comparison for a numeric kernel

Lane 5: I/O, Virtual Memory, and the Whole-Machine View​

Use this lane when ready to close the module's loop.

Target outcomes:

  • 1 hand-translation of a virtual address through a multi-level page table
  • 1 TLB-pressure benchmark with and without huge pages
  • 1 roofline sketch for a real kernel you wrote, with the "am I compute- or memory-bound?" verdict
  • 1 short memo (½ page) applying Amdahl's law to a real parallelism question

Self-Curated Problem Set​

Build a custom set with these minimums:

  • 5 disassembly annotations on functions from your own code
  • 5 cache-geometry / hit-miss problems with worked solutions
  • 3 hazard analyses of your own 4-8 line instruction streams
  • 3 measured benchmarks, each with a plain-language interpretation
  • 2 virtual-memory problems, at least one using perf or /proc/self/maps

Completion Checklist​

  • Completed at least one lane in full
  • Logged at least 10 real mistakes with corrections
  • Produced at least 4 measured benchmarks you trust within 10%
  • Annotated at least 10 disassemblies cold
  • Wrote at least one short performance memo using Amdahl's law or the roofline model