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Module Quiz

Complete this quiz after finishing all concept and practice pages. Save your answers before opening separate quiz calibration.

Current Module Questions​

Question 1: Non-Atomic Operations​

Why does counter++ need synchronization when two threads call it, even though counter is a single int?

Question 2: Race Diagnosis from a Trace​

You observe this log from two threads incrementing a shared counter that starts at 100:

T1: load counter -> 100
T2: load counter -> 100
T1: add 1, store 101
T2: add 1, store 101

What value is in memory at the end, and what concurrency bug is this?

Question 3: Race Diagnosis from a Trace (Deadlock)​

You observe this waits-for state for two threads:

Thread A: holds m1, waiting for m2
Thread B: holds m2, waiting for m1

Which Coffman condition is satisfied, and what is the smallest change that would prevent this failure going forward?

Question 4: Critical-Section Properties​

What are the three correctness properties of a mutual-exclusion protocol, and why does mutual exclusion alone not suffice?

Question 5: Spinlock vs Mutex​

A critical section takes 100 ns and runs on a 4-core machine with frequent contention. Spinlock or mutex, and why?

Question 6: Memory Orderings​

What does atomic_store_explicit(&flag, 1, memory_order_release) paired with atomic_load_explicit(&flag, memory_order_acquire) guarantee?

Question 7: Condition Variable Usage​

Explain why while (!predicate) cond_wait(&cv, &m); must use while, not if.

Question 8: Semaphore vs Mutex​

Why is a binary semaphore not a safe substitute for a mutex?

Question 9: Bounded Buffer Signal Choice​

In a producer-consumer buffer with two condition variables (not_full, not_empty), why is signal sufficient and when would you need broadcast?

Question 10: Readers-Writers Fairness​

A reader-preferring rwlock protects a config map. Writes are rare; reads arrive continuously at 10k/sec. A deploy that should take milliseconds has been waiting 30 seconds. Diagnose.

Question 11: Dining Philosophers​

Name two Coffman conditions the resource-ordering fix can break, and explain which one it actually breaks.

Question 12: ABA Problem​

Explain the ABA problem in a lock-free stack and one way to fix it.

Question 13: Memory Ordering (relaxed)​

When is memory_order_relaxed safe for an atomic counter, and when is it wrong?

Question 14: Async Races​

Can a single-threaded asyncio program have a data race? Can it have a concurrency bug?

Question 15: Lock Granularity​

A hash table with one global mutex tops out at one core of throughput under 50/50 read-write load. You shard into 64 buckets with one mutex each. The throughput rises but not 64x. Why?

Interleaved Review Questions​

Prior Module Question 1​

Why is a page table walk expensive enough to justify a TLB?

Prior Module Question 2​

What is a process, and how does it differ from a thread?

Prior Module Question 3​

State the scheduling goal trade-off between throughput and response time.

Prior Module Question 4​

Why does demand paging rely on the principle of locality?

Prior Module Question 5​

What is the difference between user mode and kernel mode, and why does it matter for correctness?

Self-Assessment and Remediation​

Mastery Level (90-100% correct):

  • Retrieval is strong; complete all module and semester evidence gates before advancing.

Proficient Level (75-89% correct):

  • Review only the missed concept pages and redo Kata 1 (bounded queue) and Kata 3 (deadlock) from scratch.

Developing Level (60-74% correct):

  • Rework Practice pages 1 and 3. Pay particular attention to Mesa semantics, Coffman conditions, and memory orderings.

Insufficient Level (<60% correct):

  • Return to the concept sequence. The interleaving habit (concepts 1-2) must be stable before anything else makes sense. Spend a full week rereading concept pages 1-6 and redoing every drill.

Progression boundary​

Quiz performance calibrates retrieval and reasoning. It does not replace runnable work, changed-case transfer, the module assessment or required semester evidence. Consult practice calibration for the additional independent cases.