| Book Exercise Lanes | exercise | 8 | Open |
| Cache Organization: Lines, Sets, Associativity, and Replacement | concept | 1 | Open |
| Cache-Aware Programming: Locality and Memory Access Patterns | concept | 2 | Open |
| Control Flow at the Machine Level: Branches, Calls, and Returns | concept | 3 | Open |
| Floating-Point Operations and Hardware Support | concept | 2 | Open |
| From C to Assembly: Reading Disassembly and Recognizing Patterns | concept | 2 | Open |
| Hazards: Data, Control, Structural — and How to Resolve Them | concept | 1 | Open |
| How the Hardware-Software Contract Shapes Performance | concept | 2 | Open |
| Instruction Set Architectures, RISC vs CISC, and the Fetch-Decode-Execute Cycle | concept | 3 | Open |
| Learning Resources | resource | 8 | Open |
| Memory-Mapped I/O, Interrupts, and DMA | concept | 3 | Open |
| Reference and Selective Reading | reference | 8 | Open |
| Registers, the Program Counter, and the Stack Pointer | concept | 2 | Open |
| Superscalar, Out-of-Order, SIMD, and Speculation | concept | 3 | Open |
| The ALU and How Numbers Are Added and Multiplied | concept | 3 | Open |
| The Classic Five-Stage Pipeline | concept | 1 | Open |
| The Memory Hierarchy: Registers, Cache, DRAM, and Disk | concept | 1 | Open |
| Virtual Memory: Pages, Page Tables, and the TLB | concept | 1 | Open |